The present invention relates to semiconductor devices, and more particularly, to semiconductor devices having a vertical channel transistor and methods of manufacturing the same.
In an integrated circuit (semiconductor) device that employs a planar type transistor, in which a gate electrode is formed on an integrated circuit (semiconductor) substrate and junction regions are formed on both sides of the gate electrode, as the integration density of the semiconductor device increases, a channel length of the transistor generally is reduced and various attempts have been made to accommodate the need for a reduced channel length. However, as the length of the channel is reduced, short channel effects, such as drain induced barrier lowering (DIBL), hot carrier effect, and/or punch through may be more likely to occur. To limit or even prevent the short channel effects, various methods have been proposed. Examples of such proposed methods include a method that reduces the depth of junction regions and a method that relatively increases the channel length by forming a groove in a channel portion. However, as the integration density of semiconductor memory devices, and in particular, dynamic random access memories (DRAM), reaches the giga bit scale, it becomes more difficult to prevent short channel effects.
To address this problem, transistors having a vertical channel have also been proposed. A DRAM cell having a vertical channel transistor and a method of manufacturing the DRAM cell are described, for example, in U.S. Pat. No. 5,817,552 (“the '552 patent”). In this method, a semiconductor substrate that includes a first layer doped with a first conductive type, a second layer doped with a second conductive type that is opposite to the first conductive type, and a third layer doped with the first conductive type is provided. Afterward, a first trench that passes through the third layer, the second layer, and the first layer is formed in the semiconductor substrate, and a second trench that crosses the first trench and passes through the third layer and the second layer is formed in the semiconductor substrate. A gate oxide film that covers at least an exposed surface of the second layer is formed, and a gate electrode that surrounds the second layer is formed on the gate oxide film. Afterward, a storage capacitor that is electrically connected to the third layer is formed on the third layer. The first through third layers are epitaxially grown on a single crystal silicon substrate and doped with predetermined dopants. The first and third layers correspond to first and second source/drain regions, respectively, and the second layer corresponds to a channel region.
As described above, in the '552 patent, the first layer corresponding to the first source/drain region, the second layer corresponding to the channel region, and the third layer corresponding to the second source /drain region are epitaxially grown on a single crystal silicon substrate. Afterward, an active pillar is formed by forming trenches and a gate electrode that surrounds the channel region is formed. As a result, the channel region in the '552 patent is defined prior to forming the active pillar. As a result, it may be difficult to locate the channel region in a specific region when the active pillar is formed. Accordingly, it may be difficult to correctly align the channel region and the gate electrode.